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 | This article needs additional citations for verification. (June 2014) |
This is a comparison of ARM instruction set architecture application processor cores designed by ARM Holdings (ARM Cortex-A) and 3rd parties. It does not include ARM Cortex-R, ARM Cortex-M, or legacy ARM cores.
ARMv7-A
This is a table comparing 32-bit central processing units that implement the ARMv7-A (A means Application[1]) instruction set architecture and mandatory or optional extensions of it, the last AArch32.
 |
| Core | Decode width |
Execution ports |
Pipeline depth |
Out-of-order execution | FPU | Pipelined VFP |
FPU registers |
NEON (SIMD) |
big.LITTLE role |
Virtualization[2] | Process technology |
L0 cache |
L1 cache |
L2 cache |
Core configurations |
Speed per core (DMIPS / MHz) |
ARM part number (in the main ID register) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ARM Cortex-A5 | 1 | 8 | No | VFPv4 (optional) | 16 × 64-bit | 64-bit wide (optional) | No | No | 40/28 nm | 4–64 KiB / core | 1, 2, 4 | 1.57 | 0xC05 | ||||
| ARM Cortex-A7 | 2 | 5[3] | 8 | No | VFPv4 | Yes | 16 × 64-bit | 64-bit wide | LITTLE | Yes[4] | 40/28 nm | 8–64 KiB / core | up to 1 MiB (optional) | 1, 2, 4, 8 | 1.9 | 0xC07 | |
| ARM Cortex-A8 | 2 | 2[5] | 13 | No | VFPv3 | No | 32 × 64-bit | 64-bit wide | No | No | 65/55/45 nm | 32 KiB + 32 KiB | 256 or 512 (typical) KiB | 1 | 2.0 | 0xC08 | |
| ARM Cortex-A9 | 2 | 3[6] | 8–11[7] | Yes | VFPv3 (optional) | Yes | (16 or 32) × 64-bit | 64-bit wide (optional) | Companion Core | No[7] | 65/45/40/32/28 nm | 32 KiB + 32 KiB | 1 MiB | 1, 2, 4 | 2.5 | 0xC09 | |
| ARM Cortex-A12 | 2 | 11 | Yes | VFPv4 | Yes | 32 × 64-bit | 128-bit wide | No[8] | Yes | 28 nm | 32–64 KiB + 32 KiB | 256 KiB, to 8 MiB | 1, 2, 4 | 3.0 | 0xC0D | ||
| ARM Cortex-A15 | 3 | 8[3] | 15/17-25 | Yes | VFPv4 | Yes | 32 × 64-bit | 128-bit wide | big | Yes[9] | 32/28/20 nm | 32 KiB + 32 KiB per core | up to 4 MiB per cluster, up to 8 MiB per chip | 2, 4, 8 (4×2) | 3.5 to 4.01 | 0xC0F | |
| ARM Cortex-A17 | 2[10] | 11+ | Yes | VFPv4 | Yes | 32 × 64-bit | 128-bit wide | big | Yes | 28 nm | 32 KiB + 32 KiB per core | 256 KiB, up to 8 MiB | up to 4 | 4.0 | 0xC0E | ||
| Qualcomm Scorpion | 2 | 3[11] | 10 | Yes (FXU&LSU only)[12] | VFPv3 | Yes | 128-bit wide | No | 65/45 nm | 32 KiB + 32 KiB | 256 KiB (single-core) 512 KiB (dual-core) |
1, 2 | 2.1 | 0x00F | |||
| Qualcomm Krait[13] | 3 | 7 | 11 | Yes | VFPv4[14] | Yes | 128-bit wide | No | 28 nm | 4 KiB + 4 KiB direct mapped | 16 KiB + 16 KiB 4-way set associative | 1 MiB 8-way set associative (dual-core) / 2 MiB (quad-core) | 2, 4 | 3.3 (Krait 200) 3.39 (Krait 300) 3.39 (Krait 400) 3.51 (Krait 450) |
0x04D 0x06F | ||
| Swift | 3 | 5 | 12 | Yes | VFPv4 | Yes | 32 × 64-bit | 128-bit wide | No | 32 nm | 32 KiB + 32 KiB | 1 MiB | 2 | 3.5 | ? | ||
| Core | Decode width |
Execution ports |
Pipeline depth |
Out-of-order execution | FPU | Pipelined VFP |
FPU registers |
NEON (SIMD) |
big.LITTLE role |
Virtualization[2] | Process technology |
L0 cache |
L1 cache |
L2 cache |
Core configurations |
Speed per core (DMIPS / MHz) |
ARM part number (in the main ID register) |
ARMv8-A
This is a table of 64/32-bit central processing units that implement the ARMv8-A instruction set architecture and mandatory or optional extensions of it. Most chips support the 32-bit ARMv7-A for legacy applications. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7-A and NEON (SIMD) chips. Some of these chips have coprocessors also include cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.
|
| Company | Core | Released | Revision | Decode | Pipeline depth |
Out-of-order execution |
Branch prediction |
big.LITTLE role | Exec. ports |
SIMD | Fab (in nm) |
Simult. MT | L0 cache | L1 cache Instr + Data (in KiB) |
L2 cache | L3 cache | Core configu- rations |
Speed per core (DMIPS/ MHz[note 1]) |
Clock rate | ARM part number (in the main ID register) | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Have it | Entries | ||||||||||||||||||||
| ARM | Cortex-A32 (32-bit)[15] | 2017 | ARMv8.0-A (only 32-bit) |
2-wide | 8 | No | 0 | ? | LITTLE | ? | ? | 28[16] | No | No | 8–64 + 8–64 | 0–1 MiB | No | 1–4+ | ? | ? | 0xD01 |
| Cortex-A34 (64-bit)[17] | 2019 | ARMv8.0-A (only 64-bit) |
2-wide | 8 | No | 0 | ? | LITTLE | ? | ? | ? | No | No | 8–64 + 8–64 | 0–1 MiB | No | 1–4+ | ? | ? | 0xD02 | |
| Cortex-A35[18] | 2017 | ARMv8.0-A | 2-wide[19] | 8 | No | 0 | Yes | LITTLE | ? | ? | 28 / 16 / 14 / 10 |
No | No | 8–64 + 8–64 | 0 / 128 KiB–1 MiB | No | 1–4+ | 1.78 | ? | 0xD04 | |
| Cortex-A53[20] | 2014 | ARMv8.0-A | 2-wide | 8 | No | 0 | Conditional+ Indirect branch prediction |
big/LITTLE | 2 | ? | 28 / 20 / 16 / 14 / 10 |
No | No | 8–64 + 8–64 | 128 KiB–2 MiB | No | 1–4+ | 2.24 | ? | 0xD03 | |
| Cortex-A55[21] | 2017 | ARMv8.2-A | 2-wide | 8 | No | 0 | big/LITTLE | 2 | ? | 28 / 20 / 16 / 14 / 12 / 10 / 5[22] |
No | No | 16–64 + 16–64 | 0–256 KiB/core | 0–4 MiB | 1–8+ | 2.65[23] | ? | 0xD05 | ||
| Cortex-A57[24] | 2013 | ARMv8.0-A | 3-wide | 15 | Yes 3-wide dispatch |
? | ? | big | 8 | ? | 28 / 20 / 16[25] / 14 |
No | No | 48 + 32 | 0.5–2 MiB | No | 1–4+ | 4.8 | ? | 0xD07 | |
| Cortex-A65[26] | 2019 | ARMv8.2-A (only 64-bit) |
2-wide | 10-12 | Yes 4-wide dispatch |
Two-level | ? | 9 | ? | SMT2 | No | 32–64 + 32–64 KiB | 0, 64–256 KiB | 0, 0.5–4 MiB | 1-8 | ? | ? | 0xD06 | |||
| Cortex-A65AE[27] | 2019 | ARMv8.2-A | ? | ? | Yes | Two-level | ? | 2 | ? | SMT2 | No | 32–64 + 32–64 KiB | 64–256 KiB | 0, 0.5–4 MiB | 1–8 | ? | ? | 0xD43 | |||
| Cortex-A72[28] | 2015 | ARMv8.0-A | 3-wide | 15 | Yes 5-wide dispatch |
Two-level | big | 8 | 28 / 16 | No | No | 48 + 32 | 0.5–4 MiB | No | 1–4+ | 6.3–7.3[29] | ? | 0xD08 | |||
| Cortex-A73[30] | 2016 | ARMv8.0-A | 2-wide | 11–12 | Yes 4-wide dispatch |
Two-level | big | 7 | 28 / 16 / 10 | No | No | 64 + 32/64 | 1–8 MiB | No | 1–4+ | 7.4–8.5[29] | ? | 0xD09 | |||
| Cortex-A75[21] | 2017 | ARMv8.2-A | 3-wide | 11–13 | Yes 6-wide dispatch |
Two-level | big | 8? | 2*128b | 28 / 16 / 10 | No | No | 64 + 64 | 256–512 KiB/core | 0–4 MiB | 1–8+ | 8.2–9.5[29] | ? | 0xD0A | ||
| Cortex-A76[31] | 2018 | ARMv8.2-A | 4-wide | 11–13 | Yes 8-wide dispatch |
128 | Two-level | big | 8 | 2*128b | 10 / 7 | No | No | 64 + 64 | 256–512 KiB/core | 1–4 MiB | 1–4 | 10.7–12.4[29] | ? | 0xD0B | |
| Cortex-A76AE[32] | 2018 | ARMv8.2-A | ? | ? | Yes | 128 | Two-level | big | ? | ? | No | No | ? | ? | ? | ? | ? | ? | 0xD0E | ||
| Cortex-A77[33] | 2019 | ARMv8.2-A | 4-wide | 11–13 | Yes 10-wide dispatch |
160 | Two-level | big | 12 | 2*128b | 7 | No | 1.5K entries | Zdroj:https://en.wikipedia.org?pojem=Comparison_of_ARMv8-A_processors||||||||
