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![]() | This article may contain an excessive amount of intricate detail that may interest only a particular audience.(April 2021) |
![]() A-series APU | |
Release date | 2011 (Original); 2017 (Zen based) |
---|---|
Codename | Fusion Desna Ontario Zacate Llano Hondo Trinity Weatherford Richland Kaveri Godavari Kabini Temash Carrizo Bristol Ridge Raven Ridge Picasso Renoir Cezanne IGP Wrestler WinterPark BeaverCreek |
Architecture | AMD64 |
Models |
|
Cores | 1 to 8 |
Transistors |
|
API support | |
Direct3D | Direct3D 11 Direct3D 12 |
OpenCL | 1.2 |
OpenGL | 4.1+ |
AMD Accelerated Processing Unit (APU), formerly known as Fusion, is a series of 64-bit microprocessors from Advanced Micro Devices (AMD), combining a general-purpose AMD64 central processing unit (CPU) and 3D integrated graphics processing unit (IGPU) on a single die.
AMD announced the first generation APUs, Llano for high-performance and Brazos for low-power devices, in January 2011. The second generation Trinity for high-performance and Brazos-2 for low-power devices were announced in June 2012. The third generation Kaveri for high performance devices were launched in January 2014, while Kabini and Temash for low-power devices were announced in the summer of 2013. Since the launch of the Zen microarchitecture, Ryzen and Athlon APUs have released to the global market as Raven Ridge on the DDR4 platform, after Bristol Ridge a year prior.
AMD has also supplied semi-custom APUs for consoles starting with the release of Sony PlayStation 4 and Microsoft Xbox One eighth generation video game consoles.
History
The AMD Fusion project started in 2006 with the aim of developing a system on a chip that combined a CPU with a GPU on a single die. This effort was moved forward by AMD's acquisition of graphics chipset manufacturer ATI[1] in 2006. The project reportedly required three internal iterations of the Fusion concept to create a product deemed worthy of release.[1] Reasons contributing to the delay of the project include the technical difficulties of combining a CPU and GPU on the same die at a 45 nm process, and conflicting views on what the role of the CPU and GPU should be within the project.[2]
The first generation desktop and laptop APU, codenamed Llano, was announced on 4 January 2011 at the 2011 Consumer Electronics Show in Las Vegas and released shortly thereafter.[3][4] It featured K10 CPU cores and a Radeon HD 6000 series GPU on the same die on the FM1 socket. An APU for low-power devices was announced as the Brazos platform, based on the Bobcat microarchitecture and a Radeon HD 6000 series GPU on the same die.[5]
At a conference in January 2012, corporate fellow Phil Rogers announced that AMD would re-brand the Fusion platform as the Heterogeneous System Architecture (HSA), stating that "it's only fitting that the name of this evolving architecture and platform be representative of the entire, technical community that is leading the way in this very important area of technology and programming development."[6] However, it was later revealed that AMD had been the subject of a trademark infringement lawsuit by the Swiss company Arctic, who used the name "Fusion" for a line of power supply products.[7]
The second generation desktop and laptop APU, codenamed Trinity was announced at AMD's 2010 Financial Analyst Day[8][9] and released in October 2012.[10] It featured Piledriver CPU cores and Radeon HD 7000 series GPU cores on the FM2 socket.[11] AMD released a new APU based on the Piledriver microarchitecture on 12 March 2013 for Laptops/Mobile and on 4 June 2013 for desktops under the codename Richland.[12] The second generation APU for low-power devices, Brazos 2.0, used exactly the same APU chip, but ran at higher clock speed and rebranded the GPU as Radeon HD 7000 series and used a new I/O controller chip.
Semi-custom chips were introduced in the Microsoft Xbox One and Sony PlayStation 4 video game consoles,[13][14] and subsequently in the Microsoft Xbox Series X|S and Sony PlayStation 5 consoles.
A third generation of the technology was released on 14 January 2014, featuring greater integration between CPU and GPU. The desktop and laptop variant is codenamed Kaveri, based on the Steamroller architecture, while the low-power variants, codenamed Kabini and Temash, are based on the Jaguar architecture.[15]
Since the introduction of Zen-based processors, AMD renamed their APUs as the Ryzen with Radeon Graphics and Athlon with Radeon Graphics, with desktop units assigned with G suffix on their model numbers (e.g. Ryzen 5 3400G & Athlon 3000G) to distinguish them from regular processors or with basic graphics and also to differentiate away from their former Bulldozer era A-series APUs. The mobile counterparts were always paired with Radeon Graphics regardless of suffixes.
In November 2017, HP released the Envy x360, featuring the Ryzen 5 2500U APU, the first 4th generation APU, based on the Zen CPU architecture and the Vega graphics architecture.[16]
Features
Heterogeneous System Architecture
AMD is a founding member of the Heterogeneous System Architecture (HSA) Foundation and is consequently actively working on developing HSA in cooperation with other members. The following hardware and software implementations are available in AMD's APU-branded products:
Type | HSA feature | First implemented | Notes |
---|---|---|---|
Optimized Platform | GPU Compute C++ Support | 2012 Trinity APUs |
Support OpenCL C++ directions and Microsoft's C++ AMP language extension. This eases programming of both CPU and GPU working together to process support parallel workloads. |
HSA-aware MMU | GPU can access the entire system memory through the translation services and page fault management of the HSA MMU. | ||
Shared Power Management | CPU and GPU now share the power budget. Priority goes to the processor most suited to the current tasks. | ||
Architectural Integration | Heterogeneous Memory Management: the CPU's MMU and the GPU's IOMMU share the same address space.[17][18] | 2014 PlayStation 4, Kaveri APUs |
CPU and GPU now access the memory with the same address space. Pointers can now be freely passed between CPU and GPU, hence enabling zero-copy. |
Fully coherent memory between CPU and GPU | GPU can now access and cache data from coherent memory regions in the system memory, and also reference the data from CPU's cache. Cache coherency is maintained. | ||
GPU uses pageable system memory via CPU pointers | GPU can take advantage of the shared virtual memory between CPU and GPU, and pageable system memory can now be referenced directly by the GPU, instead of being copied or pinned before accessing. | ||
System Integration | GPU compute context switch | 2015 Carrizo APU |
Compute tasks on GPU can be context switched, allowing a multi-tasking environment and also faster interpretation between applications, compute and graphics. |
GPU graphics pre-emption | Long-running graphics tasks can be pre-empted so processes have low latency access to the GPU. | ||
Quality of service[17] | In addition to context switch and pre-emption, hardware resources can be either equalized or prioritized among multiple users and applications. |
Feature overview
The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).
Platform | High, standard and low power | Low and ultra-low power | |||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Codename | Server | Basic | Toronto | ||||||||||||||||||||||
Micro | Kyoto | ||||||||||||||||||||||||
Desktop | Performance | Raphael | |||||||||||||||||||||||
Mainstream | Llano | Trinity | Richland | Kaveri | Kaveri Refresh (Godavari) | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir | Cezanne | ||||||||||||||
Entry | |||||||||||||||||||||||||
Basic | Kabini | Dalí | |||||||||||||||||||||||
Mobile | Performance | Renoir | Cezanne | Rembrandt | Dragon Range | ||||||||||||||||||||
Mainstream | Llano | Trinity | Richland | Kaveri | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir Lucienne |
Cezanne Barceló |
Phoenix | ||||||||||||||
Entry | Dalí | Mendocino | |||||||||||||||||||||||
Basic | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge | Pollock | |||||||||||||||||||
Embedded | Trinity | Bald Eagle | Merlin Falcon, Brown Falcon |
Great Horned Owl | Grey Hawk | Ontario, Zacate | Kabini | Steppe Eagle, Crowned Eagle, LX-Family |
Prairie Falcon | Banded Kestrel | River Hawk | ||||||||||||||
Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | 2015 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2021 | Jan 2022 | Sep 2022 | Jan 2023 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019 | Jul 2020 | Jun 2022 | Nov 2022 | ||
CPU microarchitecture | K10 | Piledriver | Steamroller | Excavator | "Excavator+"[19] | Zen | Zen+ | Zen 2 | Zen 3 | Zen 3+ | Zen 4 | Bobcat | Jaguar | Puma | Puma+[20] | "Excavator+" | Zen | Zen+ | "Zen 2+" | ||||||
ISA | x86-64 v1 | x86-64 v2 | x86-64 v3 | x86-64 v4 | x86-64 v1 | x86-64 v2 | x86-64 v3 | ||||||||||||||||||
Socket | Desktop | Performance | — | AM5 | — | — | |||||||||||||||||||
Mainstream | — | AM4 | — | — | |||||||||||||||||||||
Entry | FM1 | FM2 | FM2+ | FM2+[a], AM4 | AM4 | — | |||||||||||||||||||
Basic | — | — | AM1 | — | FP5 | — | |||||||||||||||||||
Other | FS1 | FS1+, FP2 | FP3 | FP4 | FP5 | FP6 | FP7 | FL1 | FP7 FP7r2 FP8 |
? | FT1 | FT3 | FT3b | FP4 | FP5 | FT5 | FP5 | FT6 | |||||||
PCI Express version | 2.0 | 3.0 | 4.0 | 5.0 | 4.0 | 2.0 | 3.0 | ||||||||||||||||||
CXL | — | — | |||||||||||||||||||||||
Fab. (nm) | GF 32SHP (HKMG SOI) |
GF 28SHP (HKMG bulk) |
GF 14LPP (FinFET bulk) |
GF 12LP (FinFET bulk) |
TSMC N7 (FinFET bulk) |
TSMC N6 (FinFET bulk) |
CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk) |
TSMC 4nm (FinFET bulk) |
TSMC N40 (bulk) |
TSMC N28 (HKMG bulk) |
GF 28SHP (HKMG bulk) |
GF 14LPP (FinFET bulk) |
GF 12LP (FinFET bulk) |
TSMC N6 (FinFET bulk) | |||||||||||
Die area (mm2) | 228 | 246 | 245 | 245 | 250 | 210[21] | 156 | 180 | 210 | CCD: (2x) 70 cIOD: 122 |
178 | 75 (+ 28 FCH) | 107 | ? | 125 | 149 | ~100 | ||||||||
Min TDP (W) | 35 | 17 | 12 | 10 | 15 | 105 | 35 | 4.5 | 4 | 3.95 | 10 | 6 | 12 | 8 | |||||||||||
Max APU TDP (W) | 100 | 95 | 65 | 45 | 170 | 54 | Zdroj:https://en.wikipedia.org?pojem=AMD_APU