A | B | C | D | E | F | G | H | CH | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
Type | µPGA-ZIF |
---|---|
Chip form factors | PGA |
Contacts | 906 |
FSB protocol | PCI Express |
Predecessor | FM2 |
Successor | AM4 |
Memory support | DDR3 |
This article is part of the CPU socket series |
Socket FM2+ (FM2b, FM2r2) is a zero insertion force CPU socket designed by AMD for their desktop "Kaveri" APUs (Steamroller-based) and Godavari APUs (Steamroller-based) to connect to the motherboard.[1] The FM2+ has a slightly different pin configuration to Socket FM2 with two additional pin sockets. Socket FM2+ APUs are not compatible with Socket FM2 motherboards due to the aforementioned additional pins. However, socket FM2 APUs such as "Richland" and "Trinity" are compatible with the FM2+ socket.[2]
- ECC DIMMs are supported on Socket FP3 but not supported on the Socket FM2+ package.[3]
- There are 3 PCI Express cores: one 2 ×16 core and two 5 ×8 cores. There are 8 configurable ports, which can be divided into 2 groups:
- Gfx-group: contains 2 ×8 ports. Each port can be limited to lower link widths for applications that require fewer lanes. Additionally, the two ports can be combined to create a single ×16 link.
- GPP-group: contains 1 ×4 UMI and 5 General Purpose Ports (GPP).
All PCIe links are capable of supporting PCIe 2.0 data rates. In addition, the Gfx link is capable of supporting PCIe 3.x data rate.[3]
For available chipsets consult Fusion controller hubs (FCH).
Its mobile counterpart is Socket FP3 (μBGA906).
Heatsink
The 4 holes for fastening the heatsink to the motherboard are placed in a rectangle with lateral lengths of 48 mm and 96 mm for AMD's sockets Socket AM2, Socket AM2+, Socket AM3, Socket AM3+ and Socket FM2. Cooling solutions should therefore be interchangeable.
Feature overview
The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).
Platform | High, standard and low power | Low and ultra-low power | |||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Codename | Server | Basic | Toronto | ||||||||||||||||||||||
Micro | Kyoto | ||||||||||||||||||||||||
Desktop | Performance | Raphael | Phoenix | ||||||||||||||||||||||
Mainstream | Llano | Trinity | Richland | Kaveri | Kaveri Refresh (Godavari) | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir | Cezanne | ||||||||||||||
Entry | |||||||||||||||||||||||||
Basic | Kabini | Dalí | |||||||||||||||||||||||
Mobile | Performance | Renoir | Cezanne | Rembrandt | Dragon Range | ||||||||||||||||||||
Mainstream | Llano | Trinity | Richland | Kaveri | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir Lucienne |
Cezanne Barceló |
Phoenix | ||||||||||||||
Entry | Dalí | Mendocino | |||||||||||||||||||||||
Basic | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge | Pollock | |||||||||||||||||||
Embedded | Trinity | Bald Eagle | Merlin Falcon, Brown Falcon |
Great Horned Owl | Grey Hawk | Ontario, Zacate | Kabini | Steppe Eagle, Crowned Eagle, LX-Family |
Prairie Falcon | Banded Kestrel | River Hawk | ||||||||||||||
Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | 2015 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2021 | Jan 2022 | Sep 2022 | Jan 2023 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019 | Jul 2020 | Jun 2022 | Nov 2022 | ||
CPU microarchitecture | K10 | Piledriver | Steamroller | Excavator | "Excavator+"[4] | Zen | Zen+ | Zen 2 | Zen 3 | Zen 3+ | Zen 4 | Bobcat | Jaguar | Puma | Puma+[5] | "Excavator+" | Zen | Zen+ | "Zen 2+" | ||||||
ISA | x86-64 v1 | x86-64 v2 | x86-64 v3 | x86-64 v4 | x86-64 v1 | x86-64 v2 | x86-64 v3 | ||||||||||||||||||
Socket | Desktop | Performance | — | AM5 | — | — | |||||||||||||||||||
Mainstream | — | AM4 | — | — | |||||||||||||||||||||
Entry | FM1 | FM2 | FM2+ | FM2+[a], AM4 | AM4 | — | |||||||||||||||||||
Basic | — | — | AM1 | — | FP5 | — | |||||||||||||||||||
Other | FS1 | FS1+, FP2 | FP3 | FP4 | FP5 | FP6 | FP7 | FL1 | FP7 FP7r2 FP8 |
? | FT1 | FT3 | FT3b | FP4 | FP5 | FT5 | FP5 | FT6 | |||||||
PCI Express version | 2.0 | 3.0 | 4.0 | 5.0 | 4.0 | 2.0 | 3.0 | ||||||||||||||||||
CXL | — | — | |||||||||||||||||||||||
Fab. (nm) | GF 32SHP (HKMG SOI) |
GF 28SHP (HKMG bulk) |
GF 14LPP (FinFET bulk) |
GF 12LP (FinFET bulk) |
TSMC N7 (FinFET bulk) |
TSMC N6 (FinFET bulk) |
CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk) |
TSMC 4nm (FinFET bulk) |
TSMC N40 (bulk) |
TSMC N28 (HKMG bulk) |
GF 28SHP (HKMG bulk) |
GF 14LPP (FinFET bulk) |
GF 12LP (FinFET bulk) |
TSMC N6 (FinFET bulk) | |||||||||||
Die area (mm2) | 228 | 246 | 245 | 245 | 250 | 210[6] | 156 | 180 | 210 | CCD: (2x) 70 cIOD: 122 |
178 | 75 (+ 28 FCH) | 107 | ? | 125 | 149 | ~100 | ||||||||
Min TDP (W) | 35 | 17 | 12 | 10 | 15 | 105 | 35 | 4.5 | 4 | 3.95 | 10 | 6 | 12 | 8 | |||||||||||
Max APU TDP (W) | 100 | 95 | 65 | 45 | 170 | 54 | 18 | 25 | 6 | 54 | 15 | ||||||||||||||
Max stock APU base clock (GHz) | 3 | 3.8 | 4.1 | 4.1 | 3.7 | 3.8 | 3.6 | 3.7 | 3.8 | 4.0 | 3.3 | 4.7 | 4.3 | 1.75 | 2.2 | 2 | 2.2 | 3.2 | 2.6 | 1.2 | 3.35 | 2.8 | |||
Max APUs per node[b] | 1 | 1 | |||||||||||||||||||||||
Max core dies per CPU | 1 | 2 | 1 | 1 | |||||||||||||||||||||
Max CCX per core die | 1 | 2 | 1 | 1 | |||||||||||||||||||||
Max cores per CCX | 4 | 8 | 2 | 4 | 2 | 4 | |||||||||||||||||||
Max CPU[c] cores per APU | 4 | 8 | 16 | 8 | 2 | 4 | 2 | 4 | |||||||||||||||||
Max threads per CPU core | 1 | 2 | 1 | 2 | |||||||||||||||||||||
Integer pipeline structure | 3+3 | 2+2 | 4+2 | 4+2+1 | 1+3+3+1+2 | 1+1+1+1 | 2+2 | 4+2 | 4+2+1 | ||||||||||||||||
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | ![]() |
![]() | |||||||||||||||||||||||
IOMMU[d] | — | v2 | v1 | v2 | |||||||||||||||||||||
BMI1, AES-NI, CLMUL, and F16C | ![]() |
— | ![]() | ||||||||||||||||||||||
MOVBE | — | ![]() | |||||||||||||||||||||||
AVIC, BMI2, RDRAND, and MWAITX/MONITORX | — | ![]() | |||||||||||||||||||||||
SME[e], TSME[e], ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing | — | ![]() |
— | ![]() | |||||||||||||||||||||
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT | — | ![]() |
— | ![]() | |||||||||||||||||||||
MPK, VAES | — | ![]() |
— | ||||||||||||||||||||||
SGX | — | — | |||||||||||||||||||||||
FPUs per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | |||||||||||||||||||
Pipes per FPU | 2 | 2 | |||||||||||||||||||||||
FPU pipe width | 128-bit | 256-bit | 80-bit | 128-bit | 256-bit | ||||||||||||||||||||
CPU instruction set SIMD level | SSE4a[f] | AVX | AVX2 | AVX-512 | SSSE3 | AVX | AVX2 | ||||||||||||||||||
3DNow! | 3DNow!+ | — | — | ||||||||||||||||||||||
PREFETCH/PREFETCHW | ![]() |
![]() | |||||||||||||||||||||||
GFNI | — | ![]() |
— | ||||||||||||||||||||||
AMX | — | ||||||||||||||||||||||||
FMA4, LWP, TBM, and XOP | — | ![]() |
— | — | ![]() |
— | |||||||||||||||||||
FMA3 | ![]() |
![]() | |||||||||||||||||||||||
AMD XDNA | — | ![]() |
— | ||||||||||||||||||||||
L1 data cache per core (KiB) | 64 | 16 | 32 | 32 | |||||||||||||||||||||
L1 data cache associativity (ways) | 2 | 4 | 8 | 8 | |||||||||||||||||||||
L1 instruction caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | |||||||||||||||||||
Max APU total L1 instruction cache (KiB) | 256 | 128 | 192 | 256 | 512 | 256 | 64 | 128 | 96 | 128 | |||||||||||||||
L1 instruction cache associativity (ways) | 2 | 3 | 4 | 8 | 2 | 3 | 4 | 8 | |||||||||||||||||
L2 caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | |||||||||||||||||||
Max APU total L2 cache (MiB) | 4 | 2 | 4 | 16 | 1 | 2 | 1 | 2 | |||||||||||||||||
L2 cache associativity (ways) | 16 | Zdroj:https://en.wikipedia.org?pojem=Socket_FM2+